module DATA_Bank_RAM(
  input [7:0] addra,
  input clka,
  input [31:0] dina,
  output [31:0] douta,
  input [3:0] wea
);

  reg [7:0] addra_r;
  reg [31:0] mem [255:0];
  
  always@(posedge clka) begin
    if (|wea) begin
      mem[addra][31:24] <= wea[3] ? dina : mem[addra][31:24];
      mem[addra][23:16] <= wea[2] ? dina : mem[addra][23:16];
      mem[addra][15: 8] <= wea[1] ? dina : mem[addra][15: 8];
      mem[addra][ 7: 0] <= wea[0] ? dina : mem[addra][ 7: 0];
    end
    
    if (!|wea) begin
      addra_r <= addra;
    end
  end
  
  assign douta = mem[addra_r];

endmodule
